The present disclosure relates to a semiconductor apparatus, an electronic device, and a method of manufacturing a semiconductor apparatus. More particularly, the present disclosure relates to a semiconductor apparatus, an electronic device, and a method of manufacturing a semiconductor apparatus in which joining of wirings is conducted by adhering two substrates to each other during manufacture.
A technology has been developed in which two wafers (substrates) are adhered to each other to join copper wirings formed on the wafers to each other (the joining will hereafter be referred to as “Cu—Cu joining (or Cu—Cu joint)”). In such a joining technique, the joint surfaces (Cu surfaces) of the wafers are, before joining, subjected to a reducing treatment such as chemical liquid cleaning (wet etching) or dry etching so as to remove oxygen (oxides) from the Cu surfaces, thereby exposing clean Cu surfaces (refer, for example, to Japanese Patent Laid-open No. 2007-234725, hereinafter referred to as Patent Document 1).
Patent Document 1 proposes a technology for manufacturing a solid-state imaging device wherein a semiconductor layer in which a solid-state imaging device is formed and a semiconductor layer in which a logic circuit for controlling the solid-state imaging device is formed are adhered to each other. FIGS. 15A to 15D illustrate the procedure of the solid-state imaging device manufacturing technique proposed in Patent Document 1. In addition, FIGS. 16A to 16C show the procedure of Cu—Cu joining technique carried out in adhering the two semiconductor layers to each other in the technology proposed in Patent Document 1.
In the adhering technique described in Patent Document 1, first, an SOI (silicon on insulator) substrate 410 provided with a first semiconductor layer 411 is prepared. In Patent Document 1, next, a solid-state imaging device 412 is formed in the first semiconductor layer 411, as shown in FIG. 15A. In this case, as shown in FIG. 16A, a first interlayer dielectric 413 is formed so as to cover the solid-state imaging device 412, and, further, first electrodes 414 made, for example, of copper for leading out the electrodes of the solid-state imaging device 412 is formed in the first interlayer dielectric 413.
In addition, in Patent Document 1, as shown in FIG. 15B, a logic circuit 423 for controlling the solid-state imaging device 412 is formed in a second semiconductor layer 421 different from the first semiconductor layer 411 in crystal orientation. In this instance, as shown in FIG. 16B, a second interlayer dielectric 422 is formed so as to cover the logic circuit 423, and second electrodes 424 made, for example, of copper for leading out the electrodes of the logic circuit 423 are formed in the second interlayer dielectric 422.
Subsequently, according to Patent Document 1, the first semiconductor layer 411 and the second semiconductor layer 421 are adhered to each other as shown in FIG. 15C. In this case, first, the surface of the first semiconductor layer 411 on the first interlayer dielectric 413 side (the joint surfaces of the first electrodes 414) and the surface of the second semiconductor layer 421 on the second interlayer dielectric 422 side (the joint surfaces of the second electrodes 424) are cleaned, for example, with diluted hydrofluoric acid, so as to remove oxides from the electrode surfaces. Next, as shown in FIG. 16C, alignment is carried out so that the first electrodes 414 and the second electrodes 424 face each other, followed by adhering the first semiconductor layer 411 and the second semiconductor layer 421 to each other.
Then, with the first semiconductor layer 411 and the second semiconductor layer 421 kept adhered to each other, a pressing and heating treatment is carried out, to join the first electrodes 414 and the second electrodes 424 to each other. Thereafter, that portion of the SOI substrate 410 which is on the side opposite to the first semiconductor layer 411 side is removed, to expose the solid-state imaging device 412 as shown in FIG. 15D. According to Patent Document 1, the first semiconductor layer 411 and the second semiconductor layer 421 are adhered to each other (Cu—Cu joining between the first electrodes 414 and the second electrodes 424 is carried out) in the above-mentioned manner, thereby manufacturing the solid-state imaging apparatus.